atopile

Explains the Zig-Python binding layer for developing and debugging native extensions, enhancing interoperability between Zig and Python.

Explains how the atopile compiler constructs TypeGraphs from .ato files, detailing the pipeline and key components for developers.

Facilitates the mapping of Python node/trait declarations into TypeGraph, enhancing component definition and trait management.

Explains Faebryk's TypeGraph for traversing and resolving references, enhancing type-aware queries in Python.

Explains the Zig-backed instance graph API for Python, focusing on memory management and graph traversal systems.

Facilitates KiCad file parsing and S-expression generation using Zig and Python for efficient layout synchronization.

Generates concise live progress summaries for the atopile agent based on recent tool events and changes.

Implements core runtime behavior for the Atopile sidebar agent, enabling efficient project execution and management.

Provides a reference for the .ato DSL, enabling users to author and review electronic circuit designs declaratively.

Guides users on maintaining accurate and actionable skill documentation for Claude AI, ensuring clarity and correctness in coding practices.

Provides a structured code review process for LLMs, focusing on correctness, performance, and maintainability in software development.

Facilitates LLM-focused workflows for compiling Zig, running tests, and managing configurations in a streamlined development environment.

Facilitates electronics engineering processes by managing build steps, PCB generation, and netlist outputs for efficient hardware development.

Establishes frontend standards for atopile extension webviews, covering architecture, contracts, design systems, and testing workflows.

Explains the structure and conventions of the Faebryk component library for developing and modifying hardware design modules.

Explains the Faebryk parameter solver's functionality, focusing on debugging and extending constraint solving workflows.

Facilitates authoritative ato authoring and review, guiding users through a structured design process for board development.

Facilitates spec-driven planning for complex design tasks, ensuring efficient project management and clear specifications.

Facilitates the creation of reusable, generic package projects for efficient software development and integration.

Measures and improves S-expression pipeline performance for circuit board design, focusing on throughput and memory efficiency.